1. Field of the Invention
The present invention relates to the field of semiconductors, and more particularly to a method for making a capacitor in an integrated circuit.
2. Description of the Related Art
A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance C, defined by C=kk0A/d, where k is the relative dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode surface area and d is the distance between electrodes.
As integrated circuits are continually scaled down and achieve ever higher levels of integration, the area available for memory cells is being reduced. Nevertheless, each capacitor is still required to maintain a minimum capacitance. It is therefore important that capacitors achieve a high stored charge per footprint or unit of chip area occupied. However, the use of silicon nitride (Si3N4) as the dielectric in DRAM capacitors is reaching some fundamental limitations as DRAM cells are scaled down. For example, as the Si3N4 film is continually made thinner, leakage current arising from electron tunneling through the dielectric increases. A thicker Si3N4 film is of course unacceptable since a higher distance between electrodes results in lower capacitance and a lowering of the charge able to be stored in the capacitor. Before long, such a limitation will present a barrier to the development of future generations of DRAM cells.
Several techniques have been considered for increasing the total charge capacity of the DRAM cell capacitor without significantly affecting the chip area occupied by the cell. Perhaps the most promising solution is the use of new capacitor dielectrics with higher dielectric constant k values. The decrease in capacitance that would occur were a thicker Si3N4 film to be used is offset by a higher k value. That is, the higher dielectric constant allows a thicker film to be deposited than would be practicable with Si3N4, while reducing leakage current and providing a level of capacitance that would be unattainable with Si3N4 films. One promising dielectric candidate is tantalum pentoxide (Ta2O5), which is characterized by an effective dielectric constant significantly higher than conventional dielectrics such as Si3N4. Whereas k=9 for silicon nitride, Ta2O5 has a dielectric constant of about 25. Therefore, using Ta2O5 enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement.
However, difficulties have been encountered in incorporating Ta2O5 into conventional fabrication flows. For example, after Ta2O5 is deposited on a capacitor electrode, it must be annealed at a high temperature in the presence of a highly oxidizing plasma or ambient. The high temperature converts the amorphous Ta2O5 to crystalline Ta2O5, which is preferred to achieve a higher dielectric constant. The highly oxidizing plasma or ambient reduces leakage current by ensuring maintenance of the appropriate oxygen content in the dielectric. However, the oxygen diffuses through the Ta2O5 layer and oxidizes elements of the integrated circuit including the bottom electrode of the capacitor, for example, a metal electrode, a diffusion barrier, and an underlying polycrystalline silicon (polysilicon) plug. This oxidization negates the advantages realized by utilizing Ta2O5 over Si3N4 as the capacitor dielectric in the first place. For example, oxygen diffusing through the bottom electrode oxidizes the polysilicon plug. This creates a layer of insulating SiO2 at the surface of the polysilicon plug which significantly increases resistance at the capacitor to plug interface. One solution is to employ a conductive oxygen barrier to halt the diffusion of the oxidant to structures in the capacitor and integrated circuit. This, however, has proven very difficult and costly to achieve.
Thus, there is a need for an improved method for making a DRAM cell capacitor with a crystalline Ta2O5 dielectric exhibiting low leakage while at the same time possessing a crystalline structure which provides high capacitance.
The present invention provides a method for making a DRAM cell capacitor that utilizes crystalline Ta2O5 having low leakage characteristics as the dielectric while mitigating oxidation problems. A diffusion barrier layer formed of tantalum nitride (TaN), titanium nitride (TiN), or tantalum silicon nitride (TaSiN) is formed on top of the polysilicon plug, and a bottom capacitor electrode formed from platinum, rhodium, or a platinum-rhodium alloy is formed on the diffusion barrier layer. Ta2O5 is deposited on the bottom electrode and is then annealed at least two times. One of the anneals is a high-temperature anneal in a nitrogen (N2) ambient which crystallizes Ta2O5 in an orientation that provides a high dielectric constant. Another anneal is accomplished at low temperature in an ozone (O3) ambient, achieving a reduction in leakage current. After the anneals are completed, an upper electrode of platinum, rhodium, or platinum-rhodium alloy is deposited on top of the crystalline Ta2O5.
Additional advantages and features of the present invention will be apparent from the following detailed description provided in connection with the accompanying drawings which illustrate exemplary embodiments of the invention.